A new modeling and parameter extraction methodology to represent the parasitic effects associated with shielded test structures is presented in this paper. This methodology allows to accurately account for the undesired effects introduced by the test fixture when measuring on-wafer devices at high frequencies. Since the proposed models are based on the physical effects associated with the structure, the obtained parameters allow the identification of the most important parasitic components, which lead to potential measurement uncertainty when characterizing high-frequency devices. The proposed methodology is applied to structures fabricated on different metal levels in order to point out the advantages and disadvantages in each case. The validity of the modeling and characterization methodology is verified by achieving excellent agreement between simulations and experimental data up to 50 GHz.