The growing energy footprint and environmental costs of information and communication technologies has created an awareness of the need for greener communications. However, the task of reducing the energy footprint of wireless infrastructure and terminals is daunting due to the requirements of flexibility and reconfigurability in emerging paradigms like 4G. This paper addresses the flexibility and power consumption challenges of channel filtering, which is one of the most computationally intensive kernels in the radio baseband. Power reduction strategies for programmable time-shared filters have been generally focused on the dynamic power, which has been replaced by leakage power as the dominant mode of power consumption in nanoscale CMOS devices. We investigate the role of parallelism in reducing the nanoscale CMOS power consumption. We also propose a class of programmable time-shared filters that are more area efficient than traditional folded direct form filters, when the level of parallelism is increased.