2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).
DOI: 10.1109/vdat.2005.1500057
Full text: Unavailable
In this paper, we propose a novel test architecture called the pseudo-full scan (PFS) architecture to reduce test application time and power consumption simultaneously. We also present a test generation procedure to generate a set of test patterns that is suitable for the PFS architecture. The method reduces test application time and power consumption by (1) scanning only a fraction of the flip-flops, and (2) compressing the test vector sequence into a much shorter one. Experimental results show that our method has the advantages of reducing the test application time and power dissipation compared to the conventional scan methodology.