The conductance method was applied to investigate the interface charge trap density (Dit) of solution processed ferroelectric gate thin film transistor (FGT) using indium-tin oxide (ITO)/ Pb(Zr,Ti)O3 (PZT)/Pt structure. As a result, a large value of Dit of MFS capacitor, i.e., Pt/PZT/ITO, was estimated to be 1.2 × 1014 eV−1 cm−2. This large Dit means that an interface between the ITO layer and the PZT layer is imperfect and it is one of the main reasons for the poor memory property of this FGT. By using transmission electron microscopy (TEM), this imperfect interface was clearly observed. Thus, it is concluded that improvement of this interface is critical for better memory performance.