Models created to simulate behavior of capacitors are usually generated as simplistic as possible, using data gathered at room ambient temperatures and, normally with no DC bias applied. The simplest RLC model will use the nominal capacitance of the device, the minimum ESR obtained over a broad frequency spectrum, and an inductance based on the lowest inductance measured. The simpler model is preferred because many circuits deal with hundreds of capacitors and adding these to the computational activity slows the EDA programs down tremendously. In reality, the capacitance may change dramatically with frequency, as in the case of bulk or electrolytic capacitors where the capacitance at 300 kHz could be a small fraction of the nominal capacitance. The ESR is not a constant with frequency, and may vary by decades from the minimum. Based on many capacitor manufacturers, the variation of capacitance with temperature is specified in catalogs and is moderate for most requirements, but much larger variations of capacitance with the application of DC bias is like a "dirty little secret" that very few discuss (as high as 70% capacitance loss at rated voltage). The performance of the capacitor within an application at temperatures different from 25°C, with DC bias, and at various frequencies may behave dramatically different from that indicated by the model. Methods will be presented for quickly creating SPICE models that can be imported into several EDA software tools with a little more complexity than the simplest RLC, at variable temperatures and bias conditions, centered at any frequency, thereby reducing the errors created between modeled devices and real circuit. It will also be shown how a single models can be created to represent multiple capacitors or any number in parallel; thereby eliminating the major problem with extending computational times as multiple capacitors add multiple sub-circuits or nodes in the calculations.