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ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

DOI: 10.1109/esscirc.2007.4430290

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Two-path band-pass Δ∑ modulator with 40-MHz IF 72-dB DR at 1-MHz bandwidth consuming 16 mW

Proceedings article published in 2007 by I. Galdi, E. Bonizzoni, F. Maloberti, G. Manganaro, P. Malcovati ORCID
This paper is available in a repository.
This paper is available in a repository.

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Abstract

A band-pass SigmaDelta modulator that uses two time interleaved second-order modulators and cross-coupled paths is described. Split zeros around the 40-MHz IF provide a signal band of 1 MHz with 72-dB DR and 65.1-dB peak SNR. The circuit, integrated in a 0.18-mum CMOS technology, uses a 60-MHz clock per channel. Experimental results show that the in-band region is not affected by tones caused by mismatches and that a two-tones input causes an IMD signal of 68 dBc. The power consumption is 16 mW with 1.8-V supply.