FinFETs are expected to dominate the silicon roadmap in the future. To train future VLSI engineers, the technology can be introduced into university education and research using open source predictive Process Development Kits (PDKs) . In this project the design rules of a PDK for a 14 nm standard FinFET device are explored. The concept of Middle-Of-the-Line local interconnect layers is introduced and design rules necessary for lithography techniques (off-axis illumination and double patterning) are developed. These rules are validated by running design rule checks on virtuoso layouts of standard cells and by comparing the layout density with Inverter for 45nm CMOS.