Nonvolatile flash-memory capacitors containing graphene quantum dots (GQDs) of 6, 12, and 27 nm average sizes (d) between SiO2 layers for use as charge traps have been prepared by sequential processes: ion-beam sputtering deposition (IBSD) of 10 nm SiO2 on a p-type wafer, spin-coating of GQDs on the SiO2 layer, and IBSD of 20 nm SiO2 on the GQD layer. The presence of almost a single array of GQDs at a distance of ∼13 nm from the SiO2/Si wafer interface is confirmed by transmission electron microscopy and photoluminescence. The memory window estimated by capacitance-voltage curves is proportional to d for sweep voltages wider than ± 3 V, and for d = 27 nm the GQD memories show a maximum memory window of 8 V at a sweep voltage of ± 10 V. The program and erase speeds are largest at d = 12 and 27 nm, respectively, and the endurance and data-retention properties are the best at d = 27 nm. These memory behaviors can be attributed to combined effects of edge state and quantum confinement.