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2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers.

DOI: 10.1109/vlsit.2006.1705196

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A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond

Proceedings article published in 2006 by Ki-Tae Park, Jungdal Choi, Jongsun Sel, Viena Kim, V. Kim, Changseok Kang, Yoocheol Shin, Ukjin Roh, Jintaek Park, Kinam Kim, Jang-Sik Lee ORCID, Jaesung Sim, Sanghun Jeon, Changhyun Lee, K. Kim
This paper is available in a repository.
This paper is available in a repository.

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Abstract

A new 64-cell NAND flash memory with asymmetric S/D (Source/Drain) structure for sub-40nm node technology and beyond has been successfully developed. To suppress short channel effect in NAND memory cell, asymmetric S/D consisting of optimized junction and inversion layer induced by fringe field of WL bias which is applied at NAND operation conditions is successfully utilized. 64-cell NAND string which is double number of cells used in current NAND string is also used to further reduce bit cost by achieving over 10% chip size reduction while almost maintaining MLC (multi-level-cell) NAND performance requirements