Decision feedback equalizers (DFEs) play a critical role in high-speed communications through band-limited channels. We implemented a 3-tap DFE receiver for 5-Gb/s data bandwidth. To realize a multi-tap DFE operation, a digital-control scheme is proposed that does not use analog circuits for biasing, such as DACs. In addition to the conventional loop unrolling, several techniques including combined feedback are used to reduce the latency of the feedback path. Fabricated in a 0.13-μm CMOS process, the prototype of the proposed DFE core has an area of 0.009 mm 2 and consumes 8.4 mW from a 1.2-V supply, achieving a BER of less than 10 -11 over a pair of 28-inch Nelco 4000-6 board traces.