Class D Amplifiers are widely used in portable systems such as mobile phones to achieve high efficiency. This paper presents topologies of full digital class D amplifiers in order to remove the analog DAC in the amplification path. This approach increases the playback time of embedded system. In first session, open-loop digital class D and digital modulation are discussed. The characterization of an open-loop class D prototype, using a CMOS 130 nm ASIC and a FPGA, confirms the advantage of such systems to reach a long battery life. Then, solutions with closed-loop topologies are proposed to increase linearity and power supply rejection of digital class D. Simulation results of closed-loop topologies, showing an increased in sound quality, are presented as well.