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American Institute of Physics, Journal of Applied Physics, 13(115), p. 134501

DOI: 10.1063/1.4870457

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A thermalization energy analysis of the threshold voltage shift in amorphous indium gallium zinc oxide thin film transistors under simultaneous negative gate bias and illumination

Journal article published in 2014 by Andrew J. Flewitt ORCID, M. J. Powell
This paper is available in a repository.
This paper is available in a repository.

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Abstract

Copyright 2014 American Institute of Physics. This article may be downloaded for personal use only. Any other use requires prior permission of the author and the American Institute of Physics. ; The following article appeared in J. Appl. Phys. 115, 134501 (2014) and may be found at http://scitation.aip.org/content/aip/journal/jap/115/13/10.1063/1.4870457 ; It has been previously observed that thin film transistors (TFTs) utilizing an amorphous indium gallium zinc oxide (a-IGZO) semiconducting channel suffer from a threshold voltage shift when subjected to a negative gate bias and light illumination simultaneously. In this work, a thermalization energy analysis has been applied to previously-published data on negative bias under illumination stress (NBIS) in a-IGZO TFTs. A barrier to defect conversion is extracted of 0.65 ? 0.75 eV, which is consistent with reported energies of oxygen vacancy migration. The attempt-to-escape frequency is extracted to be 106 ? 107 s?1 which suggests a weak localization of carriers in band tail states over a 20 ? 40 nm distance. Models for the NBIS mechanism based on charge trapping are reviewed and a defect pool model is proposed in which two distinct distributions of defect states exist in the a-IGZO band gap: these are associated with states that are formed as neutrally charged and 2+ charged oxygen vacancies at the time of film formation. In this model, threshold voltage shift is not due to a defect creation process, but to a change in the energy distribution of states in the band gap upon defect migration as this allows a state formed as a neutrally charged vacancy to be converted into one formed as a 2+ charged vacancy and vice versa. Carrier localization close to the defect migration site is necessary for the conversion process to take place, and such defect migration sites are associated with conduction and valence band tail states. Under negative gate bias stressing, the conduction band tail is depleted of carriers, but the bias is insufficient to accumulate holes in the valence band tail states, and so no threshold voltage shift results. It is only under illumination that the quasi Fermi level for holes is sufficiently lowered to allow occupation of valence band tail states. The resulting charge localization then allows a negative threshold voltage shift, but only under conditions of simultaneous negative gate bias and illumination, as observed experimentally as the NBIS effect. ; This work was supported by the European Community?s 7th Framework Programme under grant agreement NMP3-LA-2010-246334.