The histogram-based technique is commonly used for testing of Analog-to-Digital Converters (ADC). One of the parameters measured thanks to this technique is the Integral Non Linearity (INL). INL is also used as an initial data related to the ADC performances for the computation of a correction table in case of a LUT-based correction technique. In this context of embedded INL measurement and embedded computation of the table for LUT-based correction of ADC, we propose a new implementation establishing what we consider the best trade-off between silicon area overhead and computing time. We compare our solution with the state of the art: (a) with VHDL-level simulation we compare time performance, and (b) with FPGA placer we estimate the final surface head-out.