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39th European Conference and Exhibition on Optical Communication (ECOC 2013)

DOI: 10.1049/cp.2013.1572

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Bit Error Rate Performance Evaluation of a Silicon-on-Insulator Optical-Network-on-Chip Router in a WDM configuration

Proceedings article published in 2013 by Parini Alberto, A. Parini, Christelle Pareige, Michael J. Strain, Mathilde Gay, Marc Sorel, Gaetano Bellanca, Monique Thual, Francesco Morichetti, Laurent Bramerie, Andrea Melloni ORCID, Andrea Annoni
This paper is made freely available by the publisher.
This paper is made freely available by the publisher.

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Abstract

ISBN: 978-1-84919-759-5 ; International audience ; We present a Bit Error Rate characterization of a microring-based integrated router in Silicon-on-Insulator technology, suitable for optical networking at chip level. The switching functionalities are evaluated in a single channel (10 Gbit/s) and in a 3-channels (3x10 Gbit/s) WDM configuration. Results show, for a BER of 10-9, a maximum power penalty of 7 dB on the less performing routing path.