In this paper we describe a high performance, area-efficient implementation of Hyperelliptic Curve Cryptosystems over GF(2m). A compact Arithmetic Logic Unit (ALU) is proposed to perform multipli- cation and inversion. With this ALU, we show that divisor multiplica- tion using affine coordinates can be efficiently supported. Besides, t he required throughput of memory or Register File (RF) is reduced so that area of memory/RF is reduced. We choose hyperelliptic curves using the parameters h(x) = x and f(x) = x5 + f3x3 + x2 + f0. The performance of this coprocessor is substantially better than all previously reported FPGA-based implementations. The coprocessor for HECC over GF(283) uses 2316 slices and 2016 bits of Block RAM on Xilinx Virtex-II FPGA, and finishes one scalar multiplication in 311 µs.