We discuss the influence of negative charging on high-rate ICP etching of SiC via-holes for GaN HEMT MMICs. There is large differential etching behavior such as etch rate, etching profile, and RIE lag between S.I.- and n-SiC substrates because of the difference in wafer heating and negative charging of the sidewall during etching between both substrates. We analyze the difference in negative charging between both substrates by simulating the etching profile.