In this paper, four-bit counter with an synchronous clear and a clock enable is designed in Xilinx ISE 12.1 using Verilog module code and implemented on high performance Virtex-6 and Spartan-6 FPGA. This approach is used to implement an energy efficient BRAM counter. Energy efficient design of BRAM demands optimization and for the same reason we have used IO standards LVCMOS-15 and LVCMOS-25 for Virtex-6 (45nm) technology and Spartan-6 (40nm) technology of FPGA. As Power is directly proportional to the frequency ,with increase in frequency, there is an increase in power consumption irrespective of IO standard. When we enhance our design to FPGA the IO standard which consumes least power is the LVCMOS-15. Analysis show that using the IO Standard LVCMOS-15, the power efficiency for Spartan-6 FPGA is improved by 98.171%, 98.036%, 97.099%, 96.712% and 96.070% for 10MHz, 100MHz, 500MHz, 700MHz and 1000MHz respectively over Virtex-6 FPGA. Thus using Spartan-6 with IO Standard LVCMOS-15 yields better results for power efficiency than using Spartan-6 with and without IO Standard LVCMOS-25, Virtex-6 with and without using IO standard LVCMOS-15 and LVCMOS-25.