Published in
Institute of Electrical and Electronics Engineers, IEEE Open Journal of Circuits and Systems, (2), p. 46-55, 2021
DOI: 10.1109/ojcas.2020.3034819
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A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects
Journal article published in 2021 by
Can Wang 
,
Li Wang ,
Zhao Zhang ,
Milad Kalantari Mahmoudabadi ,
Weimin Shi,
C. Patrick Yue
,
Li Wang ,
Zhao Zhang ,
Milad Kalantari Mahmoudabadi ,
Weimin Shi,
C. Patrick Yue
This paper was not found in any repository, but could be made available legally by the author.
Full text: Unavailable
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