Published in
Institute of Electrical and Electronics Engineers, IEEE Transactions on Electron Devices, 12(67), p. 5368-5373, 2020
2020 IEEE Symposium on VLSI Technology, 2020
DOI: 10.1109/vlsitechnology18217.2020.9265104
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Scalability of Quad Interface p-MTJ for 1X nm STT-MRAM With 10-ns Low Power Write Operation, 10 Years Retention and Endurance > 10¹¹
Journal article published in 2020 by
Sadahiko Miura 
,
Koichi Nishioka ,
Hiroshi Naganuma,
Nguyen T. V. A.,
T. V. A. Nguyen,
Hiroaki Honjo ,
Shoji Ikeda ,
Toru Yoshizuka,
Toshinari Watanabe,
Hirofumi Inoue,
Masaaki Niwa,
Takaho Tanigawa,
Yasuo Noguchi,
T. Yoshiduka,
Mitsuo Yasuhira
and other authors.
,
Koichi Nishioka ,
Hiroshi Naganuma,
Nguyen T. V. A.,
T. V. A. Nguyen,
Hiroaki Honjo ,
Shoji Ikeda ,
Toru Yoshizuka,
Toshinari Watanabe,
Hirofumi Inoue,
Masaaki Niwa,
Takaho Tanigawa,
Yasuo Noguchi,
T. Yoshiduka,
Mitsuo Yasuhira
and other authors.
This paper was not found in any repository, but could be made available legally by the author.
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