Published in
Institute of Electrical and Electronics Engineers, IEEE Journal of Solid-State Circuits, 10(55), p. 2734-2746, 2020
DOI: 10.1109/jssc.2020.3005780
Links
Tools
A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator
This paper was not found in any repository, but could be made available legally by the author.
Full text: Unavailable
Published version:
archiving forbidden
Data provided by 