To improve the performance of phase-locked loops (PLLs) under adverse grid conditions, incorporating different filtering techniques into their structures have been proposed in the literature. These filtering techniques can be broadly classified into in-loop and preloop filtering techniques depending on their position in the PLL structure. Inspired from the concept of delayed signal cancellation (DSC), the idea of cascaded DSC (CDSC) has recently been introduced as an effective solution to improve the performance of the PLL under adverse grid conditions. However, the focus has been on the application of CDSC operator as the prefiltering stage of PLL, and little work has been conducted on its application as the in-loop filtering stage of PLL. This paper provides a detailed analysis and design of dqCDSC-PLL (PLL with in-loop dq-frame CDSC operator). The study is started with an overview of this PLL. A systematic design method to fine tune its control parameters is then proposed. The performance of the dqCDSC-PLL under different grid scenarios is then evaluated in detail. It is then shown that how using the proportional-integral-derivative controller as the loop filter can improve the response time of dqCDSC-PLL. A detailed comparison between the dqCDSC-PLL and moving average filter (MAF) based PLL (MAF-PLL) is then carried out. Through a detailed mathematical analysis, it is also shown that these PLLs are equivalent under certain conditions. The suggested guidelines in this paper make designing the dqCDSC-PLL a simple and straightforward procedure. Besides, the analysis performed in this paper provides a useful insight for designers about the advantages/disadvantages of dqCDSC-PLL for their specific applications.