Vertex detectors for High Energy Physics experiments require pixel detectors featuring high spatial resolution, very good signal to noise ratio and radiation hardness. A way to face new challenges brought by the upgrades of Large Hadron Collider (LHC) at CERN, called High Luminosity LHC (HL-LHC) and ATLAS future hybrid pixel vertex detectors is to use the emerging 3D Integrated Technologies. However, commercial offers of such technologies are only very few and the 3D designer's choice is as a consequence strongly constrained. Moreover, as radiation hardness and in particular SEU tolerance of configuration registers is a crucial issue for HL-LHC vertex detectors, and as commercial data on this topic are always missing, a reliable qualification program is to be developed for any candidate technology. We present here the test of GlobalFoundries 130 nm chips processed by the Tezzaron Company, submitted within the 3D-IC consortium. Reliability and influence on the integrated devices behavior of Bond Interface (BI) and Through Silicon Via (TSV) connections, both needed for the 3D integration process, has also been addressed by the tests.