Published in

ECS Meeting Abstracts, 27(MA2019-02), p. 1241-1241, 2019

DOI: 10.1149/ma2019-02/27/1241

American Association for the Advancement of Science, Science, 6440(364), p. 570-574, 2019

DOI: 10.1126/science.aaw5581

Links

Tools

Export citation

Search in Google Scholar

Parallel programming of an ionic floating-gate memory array for scalable neuromorphic computing

This paper is made freely available by the publisher.
This paper is made freely available by the publisher.

Full text: Download

Green circle
Preprint: archiving allowed
Green circle
Postprint: archiving allowed
Red circle
Published version: archiving forbidden
Data provided by SHERPA/RoMEO

Abstract

Neuromorphic computers could overcome efficiency bottlenecks inherent to conventional computing through parallel programming and read out of artificial neural network weights in a crossbar memory array. However, selective and linear weight updates and <10nA read currents are required for learning that surpasses conventional computing efficiency. We introduce an ionic floating-gate memory array [1] based upon a polymer redox transistor connected to a volatile conductive-bridge memory (CBM). Selective and linear programming of a transistor array is executed in parallel by overcoming the bridging threshold of the CBMs. Synaptic weight readout with currents <10nA is achieved by diluting the conductive polymer in an insulating channel to decrease the conductance. The redox transistors endure > 109 ‘read-write’ operations and support > 1MHz ‘read-write’ frequencies. [1] Fuller et. al. Science, 2019 (in press)