Published in
Institute of Electrical and Electronics Engineers, IEEE Electron Device Letters, 5(40), p. 694-697, 2019
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A Compact Model for Border Traps in Lateral MOS Devices with Large Channel Resistance
Journal article published in 2019 by
Ruiyuan Yin 
,
Yue Li,
Wei Lin ,
Cheng P. Wen,
Yilong Hao,
Yunyi Fu,
Maojun Wang
,
Yue Li,
Wei Lin ,
Cheng P. Wen,
Yilong Hao,
Yunyi Fu,
Maojun Wang
This paper was not found in any repository, but could be made available legally by the author.
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