Published in
Institute of Electrical and Electronics Engineers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(27), p. 2375-2386, 2019
DOI: 10.1109/tvlsi.2019.2918385
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A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement
Journal article published in 2019 by
Fazal Hameed 
,
Jeronimo Castrillon
,
Jeronimo Castrillon
This paper was not found in any repository, but could be made available legally by the author.
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