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2003 IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003. Proceedings. (ICASSP '03).

DOI: 10.1109/icassp.2003.1202362

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Optimized low-power synchronizer design for the IEEE 802.11(a) standard

Proceedings article published in 2003 by Milos Krstic ORCID, Alfonso Troya, Koushik Maharatna, Eckhard Grass
This paper was not found in any repository, but could be made available legally by the author.
This paper was not found in any repository, but could be made available legally by the author.

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Abstract

The authors propose a low-power synchronizer design for the IEEE 802.11a standard capable to estimate frequency offsets in the range ±468 kHz (80 ppm @ 5.8 GHz) with very simple and effective frame detection and timing synchronization. The core area of the design after layout is 13 mm2, including the CORDIC and FFT processors, with a total estimated power consumption of 140 mW.