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IOP Publishing, Japanese Journal of Applied Physics, 8S2(55), p. 08PD01, 2016

DOI: 10.7567/jjap.55.08pd01

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Material and device engineering in fully depleted silicon-on-insulator transistors to realize a steep subthreshold swing using negative capacitance

Journal article published in 2016 by Hiroyuki Ota, Shinji Migita, Junichi Hattori, Koichi Fukuda ORCID, Akira Toriumi
This paper was not found in any repository, but could be made available legally by the author.
This paper was not found in any repository, but could be made available legally by the author.

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Abstract

Abstract This paper discusses material and device engineering in field-effect transistors (FETs) with HfO2-based ferroelectric gate insulators to attain a precipitous subthreshold swing (SS) by exploiting negative capacitance. Our physical analysis based on a new concept of a negative dielectric constant reveals that fully depleted silicon-on-insulator (FD-SOI) channels with a modest remnant polarization P r (3 µC/cm2 at most) are more suitable for realizing SS < 60 mV/decade than a higher P r of 10 µC/cm2, which is commonly reported for HfO2-based ferroelectric materials. We also confirm SS < 60 mV/decade in more than 5 orders of the subthreshold current in FD-SOI FETs with ferroelectric HfO2 gate insulators by device simulation.