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Institute of Electrical and Electronics Engineers, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 4(38), p. 678-691, 2019

DOI: 10.1109/tcad.2018.2821561

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A high throughput acceleration for hybrid neural networks with efficient resource management on FPGA

This paper was not found in any repository, but could be made available legally by the author.
This paper was not found in any repository, but could be made available legally by the author.

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