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IOP Publishing, Japanese Journal of Applied Physics, 7(55), p. 070303, 2016

DOI: 10.7567/jjap.55.070303

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Scaling limit for InGaAs/GaAsSb heterojunction double-gate tunnel FETs from the viewpoint of direct band-to-band tunneling from source to drain induced off-characteristics deterioration

Journal article published in 2016 by Wenbo Lin, Shinjiro Iwata, Koichi Fukuda ORCID, Yasuyuki Miyamoto
This paper was not found in any repository, but could be made available legally by the author.
This paper was not found in any repository, but could be made available legally by the author.

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Abstract

Abstract In this paper, we propose a method to classify the tunneling currents using simulations. The main objective is to investigate the effects of the direct source-to-drain tunneling, which is undesirable, in the case of devices with extremely short channels. We performed the classification of tunneling currents in InGaAs/GaAsSb heterojunction double-gate tunnel FETs based on this method, and we found that the direct-tunneling component increased dramatically in short-channel cases. The channel length must be 20 nm or longer, in case of InGaAs/GaAsSb heterojunction double-gate tunnel FETs, to limit the off-current within 10 pA/µm, which is required as per the ITRS LP.