Published in
Institute of Electrical and Electronics Engineers, IEEE Transactions on Power Electronics, 12(31), p. 8042-8045, 2016
DOI: 10.1109/tpel.2016.2562030
2016 IEEE Applied Power Electronics Conference and Exposition (APEC)
DOI: 10.1109/apec.2016.7467948
Links
- ORCID
- Institute of Electrical and Electronics Engineers
- Institute of Electrical and Electronics Engineers
Tools
A Novel DBC Layout for Current Imbalance Mitigation in SiC MOSFET Multichip Power Modules
This paper was not found in any repository, but could be made available legally by the author.
Full text: Unavailable
Published version:
archiving forbidden
Data provided by 