456 papers found
Refreshing results…
Circuit-Level Simulation of a CNTFET With Unevenly Positioned CNTs by Linear Programming
Design of a Nanometric CMOS Memory Cell for Hardening to a Single Event With a Multiple-Node Upset
Concurrent Error Detection of Binary and Nonbinary OLS Parallel Decoders
Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing
A low-power, high-performance approximate multiplier with configurable partial error recovery
HSPICE macromodel of a programmable metallization cell (PMC) and its application to memory design
New 4T-based DRAM cell designs
A hybrid non-volatile SRAM cell with concurrent SEU detection and correction
nexact Floating-Point Adder for Dynamic Image Processing
F-DICE: A multiple node upset tolerant flip-flop for highly radioactive environments
A novel scheme for concurrent error detection of OLS parallel decoders
New Metrics for the Reliability of Approximate and Probabilistic Adders
Analysis of Error Masking and Restoring Properties of Sequential Circuits
Approximate XOR/XNOR-based adders for inexact computing
On the drift behaviors of a phase change memory (PCM) cell
Design and evaluation of two MTJ-based content addressable non-volatile memory cells
A PCM-based TCAM cell using NDR
Testing a Nanocrossbar for Multiple Fault Detection
On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment
Message From the New Editor-in-Chief
Missing publications? Read more about our data sources.