Jinjuan Xiang
0000-0001-9728-5994
11 papers found
Refreshing results…
Endurance Improvement of Si FeFET by a Fully CMOS-Compatible Process: Insertion of HfO x at Hf0.5Zr0.5O2/SiO x Interface to Suppress Oxygen Vacancy Generation
A Novel 3D NOR Flash With Single-Crystal Silicon Channel: Devices, Integration, and Architecture
Vertical C-Shaped-Channel Nanosheet FETs Featured With Precise Control of Both Channel-Thickness and Gate-Length
Experimental Extraction and Simulation of Charge Trapping During Endurance of FeFET With TiN/HfZrO/SiO2/Si (MFIS) Gate Structure
Ferroelectric Vertical Gate-All-Around Field-Effect-Transistors With High Speed, High Density, and Large Memory Window
Impact of Interlayer and Ferroelectric Materials on Charge Trapping During Endurance Fatigue of FeFET With TiN/Hf x Zr1-x O2/Interlayer/Si (MFIS) Gate Structure
The Effect of Interface Traps at the Si/SiO₂ Interface on the Transient Negative Capacitance of Ferroelectric FETs
Vertical Sandwich GAA FETs With Self-Aligned High-k Metal Gate Made by Quasi Atomic Layer Etching Process
Understanding the mechanisms impacting the interface states of ozone-treated high-k/SiGe interfaces
Impact of Charges at Ferroelectric/Interlayer Interface on Depolarization Field of Ferroelectric FET With Metal/Ferroelectric/Interlayer/Si Gate-Stack
Vertical Sandwich Gate-All-Around Field-Effect Transistors With Self-Aligned High-k Metal Gates and Small Effective-Gate-Length Variation
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