Takafumi Fukushima
0000-0003-2303-8178
Tohoku University
198 papers found
Refreshing results…
Fully-Filled, Highly-Reliable Fine-Pitch Interposers with TSV Aspect Ratio >10 for Future 3D-LSI/IC Packaging
Mechanical and Electrical Characterization of FOWLP-Based Flexible Hybrid Electronics (FHE) for Biomedical Sensor Application
500 nm-sized Ni-TSVwith Aspect Ratio 20 for Future 3D-LSIs_A Low-Cost Electroless-Ni Plating Approach
Multichip thinning technology with temporary bonding for multichip-to-wafer 3D integration
Mechanical Characterization of FOWLPBased Flexible Hybrid Electronics (FHE) for Biomedical Sensor Application
X-ray computed tomography studies on directed self-assembly formed vertical nanocylinders containing metals for 3D LSI applications—characterization technique-dependent reliability issues
Noise Propagation through TSV in Mixed-Signal 3D-IC and Investigation of Liner Interface with Multi-Well Structured TSV
Development of Eccentric Spin Coating of Polymer Liner for Low-Temperature TSV Technology With Ultra-Fine Diameter
High-Thermoresistant Temporary Bonding Technology for Multichip-to-Wafer 3-D Integration With Via-Last TSVs
Advanced Tape Expansion/Assembly Technology for FOWLP and Micro-LED Display
Flexible Hybrid Electronics Technology Using Die-First FOWLP for High-Performance and Scalable Heterogeneous System Integration
Continuous Peripheral Blood Pressure Measurement with ECG and PPG Signals at Fingertips
Process Integration for FlexTrateTM
Capillary Self-Assembly Based Multichip-to-Wafer System Integration Technologies
Charge-Trap-Free Polymer-Liner Through-Silicon Vias for Reliability Improvement of 3D ICs
Extremely Flexible (1mm Bending Radius) Biocompatible Heterogeneous Fan-Out Wafer-Level Platform with the Lowest Reported Die-Shift (<6 µm) and Reliable Flexible Cu-Based Interconnects
Self-Assembly Technologies for FlexTrate™
TSV liner dielectric technology with spin-on low-k polymer
Development of integrated photoplethysmographic recording circuit for trans-nail pulse-wave monitoring system
Tunnel field-effect transistor charge-trapping memory with steep subthreshold slope and large memory window
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