Jongsun Park
0000-0003-3251-0024
109 papers found
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Sensitivity-Based Error Resilient Techniques With Heterogeneous Multiply–Accumulate Unit for Voltage Scalable Deep Neural Network Accelerators
A Perspective on Test Methodologies for Supervised Machine Learning Accelerators
An Energy-efficient On-chip Learning Architecture for STDP based Sparse Coding
Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge Scheme
Design of Processing-“Inside”-Memory Optimized for DRAM Behaviors
Sensitivity based Error Resilient Techniques for Energy Efficient Deep Neural Network Accelerators
Mosaic-CNN: A Combined Two-Step Zero Prediction Approach to Trade off Accuracy and Computation Energy in Convolutional Neural Networks
A novel one-body dual laser profile based vibration compensation in 3D scanning
Low Cost Hardware Implementation of LEA-128 Encryption using Bit-Serial Technique
Spin Orbit Torque-RAM Write Energy Reduction with Self-Verification Scheme
A Low-Latency and Area-Efficient Gram–Schmidt-Based QRD Architecture for MIMO Receiver
Spin Orbit Torque Device based Stochastic Multi-bit Synapses for On-chip STDP Learning
Complementary logic operation based on electric-field controlled spin–orbit torques
Spike Counts Based Low Complexity Learning with Binary Synapse
Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme
Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging Scheme
Charge-Recycling based Redundant Write Prevention Technique for Low Power SOT-MRAM
Energy Efficient Canny Edge Detector for Advanced Mobile Vision Applications
Continuous cervical epidural block
Low Cost Convolutional Neural Network Accelerator Based on Bi-Directional Filtering and Bit-Width Reduction
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