Published in
2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
DOI: 10.1109/ulis.2016.7440059
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Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET
Proceedings article published in 2016 by
R. Berthelon,
F. Andrieu,
S. Ortolland,
R. Nicolas,
T. Poiroux,
E. Baylac,
D. Dutartre,
E. Josse,
A. Claverie,
M. Haond
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