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Ynthesis and packaging of nanocrystals by ultra low energy ion implantation for applications in electronics, optics and plasmonics

This paper is available in a repository.
This paper is available in a repository.

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Abstract

Ultra low energy ion implantation is a flexible and fully Si CMOS compatible technique to fabricate 2D arrays of nanocrystals of controlled size and density, buried in dielectrics and at a tuneable distance from the surface. Si nanocrystals, fabricated by this technique, have been used to store charges and integrated into CMOS based devices, to improve the performances of the floating gate (flash) memories. Recently, planes of Ag nanocrystals have been produced following the same route, foreseeing the possibility to fabricate "SERS-ready" substrates. It is the goal of this chapter to review the main materials science aspects of the fabrication of 2D arrays of nanocrystals of controllable sizes in dielectric layers and at tuneable distances from their surfaces or from electrodes by using ultra low energy ion implantation. The basic rules for the selection of appropriate implant/matrix combinations, for the fine tuning of the depth-positioning and of the density of 2D arrays of NCs together with problems related to humidity penetration and solutions for optimized passivation of the NCs, are among the discussed topics.