Si-nanocrystal memory devices aiming at low-voltage non-volatile memory applications are explored. The devices consist of a single metal-oxide-semiconductor field-effect-transistor with silicon nanocrystals fabricated through ultra-low-energy (1 keV) Si implantation of the gate oxide (7 nm in thickness) and subsequent thermal annealing. Process issues like boron contamination and parasitic currents that affect the threshold voltage and transfer characteristics of the intended devices are discussed in terms of device structure, process parameter and device simulation. It is shown that these issues can be overcome under appropriate process modifications. Threshold shift of about 2 V are obtained for a 10 ms +9 V/−9 V pulse regime where both electron and hole trapping occur. Neither degradation, nor drift in memory window is detected after 1.5 × 106 10 ms +9 V/−9 V cycles. Charge retention measurements reveal that the de-trapping mechanism of stored holes is faster than that of trapped electrons and independent on the temperature. Memory operation with reduced hole trapping, herein demonstrated for a 10 ms +9 V/−7 V regime leading to a 0.3 V 10-year extrapolated memory window at 150 °C, should be preferred for long non-volatile retention of years.