2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip
DOI: 10.1109/nocs.2012.26
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This paper targets the development of a verification methodology for Networks on Chip. We advocate the use of formal methods to guarantee an unambiguous expression of the specifications. A previous theorem proving based solution enables the verification of high-level properties for NoC communication algorithms, it deliberately addresses abstract NoC descriptions and ignores implementation details. We suggest here a complementary approach, oriented toward Assertion-Based Verification, that focuses on the verification of RT level implementations, also applicable to the on-line checking of robustness properties.