To understand the behavior of silicon nitride capping etch stopping layer stressors in nanoscale microelectronics devices, a simplified structure mimicking typical transistor geometries was studied. Elastic strains in the silicon substrate were mapped using dark-field electron holography. The results were interpreted with the aid of finite element method modeling. We show, in a counterintuitive sense, that the stresses developed by the film in the vertical sections around the transistor gate can reach much higher values than the full sheet reference. This is an important insight for advanced technology nodes where the vertical contribution of such liners is predominant over the horizontal part.